Overcoming access latency inefficiency in memories for packet switched networks

ABSTRACT

A method buffering packets in a packet switching network (FIG.  5 ) includes receiving a packet from the network; splitting the packet into a plurality of PDUs; stripping at least some of the PDUs over a plurality of memory banks; ( 18 ) retrieving the PDUs from the memory banks: and at least temporarily storing the retrieved PDUs in the sequence they are to be transmitted. An apparatus for implementing the method is also disclosed.

This application claims the benefit of provisional application Ser. No.60/350,611 filed Nov. 13, 2001.

BACKGROUND

1. Field of the Invention

The present invention relates to memory control and the use of memories,especially in packet switched telecommunications networks and at nodesin such networks.

2. State of the Art

During scheduling of data transfer of a packet switched network atraffic manager needs to buffer quite a large amount of data to allowscheduling in case of heavy traffic and to equalize bursty traffic.Failure to do this can lead to dropping packets. Also, packets do notnecessarily leave a node in the same order they arrive which alsorequires buffering.

The large amount of buffering needed at a packet switched network nodecan be solved by the use of cost-effective off-chip DRAM-basedtechnology. Use of DRAM is associated with access latency. Regardless oftechnologies used to increase the bandwidth per pin (such as Double DataRate (DDR) SDRAM or RAMBUS DRAM (RDRAM)), a main bottleneck in any DRAMimplementation is the large bank turnaround time, which is currentlyaround 60 ns. The bank turnaround time limits the frequency of accessingdifferent (random) rows within a single bank, and therefore limits thedata bus utilization drastically. For this reason, DRAM chips havemultiple banks (typically 2 or 4) to increase the best-case bus usage,but this does not on its own change the worst-case bus usage.

A DRAM channel is defined as a single logical set of address (+ control)and data lines. A single channel has a particular width, which is thenumber of data lines and can be implemented using multiple DRAMcomponents. A DRAM access cycle is defined as the sequence of operationsperformed on the address and data lines to do a particular random reador write request. The DRAM access cycle turnaround for a given amount ofdata is the time it takes between the start of either a random read orwrite request for that amount of data and the start of the next possiblerandom read or write request. A DRAM bank is defined as a subset of aDRAM channel that has an independent access cycle. For example, if achannel has 4 banks, then up to 4 access cycles can be performedsimultaneously. However, all banks within a particular channel share alladdress, control and data lines.

It is an object of the present invention to provide improved performanceof a memory which is subject to access latency.

It is an object of the present invention to provide a memory structurehaving improved performance and for use in packet switched networks,especially in nodes of such a network.

SUMMARY OF THE INVENTION

One aspect of the present invention is a bank-striping for writing. Thismay be combined with a method for simultaneous packet de-queuing. Thiscombination may guarantee up to 100% bus utilization efficiency forwriting while arbitrarily increasing the statistical performance forreading efficiency. The buffering unit may be advantageously used in anode of a packet switched network, such as a landline packet switchednetwork or a mobile telecommunications network. The term “packetswitching” includes systems having variable length packets (e.g. packetssent in accordance with an IP protocol on the Internet) or constantlength packets, sometimes called “cells” (e.g. as sent in an ATMsystem).

The present invention provides a packet buffering unit for a packetswitched system comprising:

a packet receive unit for receiving packets from the network and forsplitting these packets into packet data units (PDU);

a plurality of memory banks;

a memory controller for striping at least some of the PDUs of a packetover the memory banks;

a packet management unit for retrieving PDUs stored in the memory banksand associated with a packet; and

a transmission queue means for at least temporarily storing theretrieved PDUs in the sequence they are to be transmitted. The memorybanks are preferably split up into buffers. Where a packet has more databits than can be stored in one buffer the packet may first be split upinto packet segments whereby each segment is able to be buffered in onebuffer. Each packet segment is then split up into PDUs. The presentinvention may also include a packet scheduler for scheduling a packetfor transmission. The packet scheduler co-operates with the packetmanagement unit or is a part thereof and the combination provides thecomplete service of scheduling and retrieving packets for transmission.The packet buffering unit may be implemented in hardware or a mixture ofhardware and at least one programmable element such as a PLA, PLA, GateArray, FGPA, or a microprocessor.

The present invention also includes a method of buffering packets in apacket switched system comprising:

receiving packets from the network and splitting these packets intopacket data units (PDUs);

striping at least some of the PDUs of a packet over a plurality ofmemory banks;

retrieving PDUs stored in the memory banks and associated with a packet,and

at least temporarily storing the retrieved PDUs in the sequence they areto be transmitted.

The present invention is particularly advantageous when the bank accessturnaround time is non-zero.

The present invention also includes software computer program productsfor carrying out any of the methods of the present invention when run ona suitable processing engine.

The present invention will now be described with reference to thefollowing drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of a packet handler at a node of apacket switched network.

FIG. 2 is a schematic representation of a fixed rate schedule controlmechanism which may be used with the present invention.

FIG. 3 is a schematic representation of a packet buffering processaccording to an embodiment of the present invention.

FIG. 4 is a schematic representation of a packet transmit processaccording to an embodiment of the present invention.

FIG. 5 is a schematic representation of a hardware based packetbuffering unit according to an embodiment of the present invention.

FIG. 6 is a schematic representation of a software based packetbuffering unit according to yet another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described with reference to certainembodiments and drawings but the skilled person will appreciate that thepresent invention has wider application than these embodiments anddrawings which are provided as examples only of the invention.

A buffering subsystem is shown schematically in FIG. 1, e.g. as may beimplemented at a node of a packet switched network. The packet switchednetwork may be any packet switched network such as a landlinetelecommunications network or a mobile radio telecommunications network.Packet switched networks can be divided into those which allow anindependent decision of the routing of a packet at each node (datagramsystem) and those which set up a virtual circuit through the network anddeliver packets along these virtual networks (virtual circuit system).Further, packet switched systems may be divided into those which usevariable length packets and those which use constant length packets,sometimes called cells. The present invention may find advantageous usewith any of the above packet switched systems. No limitation on thetypes of packet switched system is anticipated which can be used withthe present invention. In any such system packets need to be buffered atvarious places in the system in order to deal with varying transmissionrates. Such places may be nodes of a telecommunications network of whichswitches, routers, base stations, gateways, terminals, servers, userequipment, modems, mobile telephones, repeaters are a non-limiting list.Packets enter the subsystem (1), with additional information such asdestination queue. The Packet Receive block (A) requests (2) one or morefree buffers from the Buffer Management block (D). The packet getsen-queued (3) by means of a descriptor, for instance, into the PacketQueue Management block (F), while the packet itself is sent (4) to thememory e.g. DRAM, controller (B) which stores (5) it in a memory such asa DRAM (C).

The scheduler (W, see FIG. 4) which may be included within the PacketQueue Management block (F) or may be separate from it schedules a packetfor transmission and de-queues the packet descriptor from its datastructures. This gets forwarded (6) to the Packet Transmit block (E),which requests (7) the DRAM controller (B) to retrieve (8) the packetfrom DRAM (C). Subsequently, the buffer or buffers containing the packetare freed (9), and the packet is transmitted (10).

Embodiments of the present invention comprise apparatus and methods tobe implemented in the shaded blocks in FIG. 1, but do not necessarilyimpose any restrictions on DRAM technology or Packet Queue Managementmechanisms. Preferably, the scheduling of packets in accordance with thepresent invention is not influenced, nor is the order of transmittedpackets changed from the order in which they have been scheduled. Theorder in which packets arrive is not necessarily the order in which theyare transmitted. In fact, the present invention is particularly usefulwhen the transmit order is not the same as the receive order. Suchchanges of order can occur when different packets have differentpriorities, for instance. In such a system high priority packets will bebrought forward in the transmission queue compared with packets havinglower priorities.

In accordance with a packet storage model in accordance with anembodiment of the present invention, the incoming packets are split intofixed-size chunks or Packet Data Units (PDU) before storage. Embodimentsof the present invention can guarantee a fixed rate for writing PDUs tomemory, regardless of whether they are from a single-PDU packet or alarger packet. In this way, the fixed rate for storing PDUs ispreferably related to the maximum packet arrival rate. Generally, it canbe assumed that this maximum rate is provided by minimum-sized packets.The PDU size itself is freely selectable but should preferably berelated to the size of a minimum-sized packet, but may be larger.

The memory is organized in banks. All banks on their own can guarantee arate for writing and reading PDUs to random memory locations within thatbank. A bank by this definition maps on a DRAM bank. However, there canbe more banks in total when multiple memory channels are used. A PDU ispreferably always written or read in one burst. For memory management,the position of a PDU in memory can be the smallest addressable unitcalled a PDU location. The width of a single DRAM channel is chosen sothat the bandwidth provided by the data lines can be maximally used.This takes into account PDU size, number of banks per channel, and theaccess cycle turnaround time for a PDU size of data. In this way asingle channel will offer a certain PDU rate. The number of channels isthen chosen to achieve the necessary overall PDU rate, where n channelshave a PDU rate of n times the PDU rate of a single channel.

The memory controller itself can be implemented using a fixed schedulebut the present invention is not limited thereto. For example, for aconventional packet buffering system, the requirement is that eachpacket should be stored and retrieved once, and thus writing and readingbandwidth must be equal. A simple fixed schedule that can be developedthis way is shown in FIG. 2. In this schedule, the memory controllerprovides, per bank, a queue for PDUReadRequests and one forPDUWriteRequests as shown in FIG. 2. The queues may be implemented asFIFO registers for read requests (G-J) and write requests (K-N). Allqueues are emptied at the same speed, e.g. by polling each FIFO G-J andK-N in turn. It is however not necessary that the memory controllerimplements a schedule like this. The only requirement is that it usesthe DRAM memory bandwidth maximally when provided with a bounded backlogof requests in all of these queues. This is the case for this simplescheduler, for a backlog of 1 request in all the request queues. Theresult of this organization is that the memory of n banks is accessedusing n read and n write request queues (G-J, K-N) which store requestsfor PDU sizes of data, as shown in FIG. 2 for n=4.

Other useful schedules which are examples of schedules which may be usedwith the present invention include 1 write process combined with 2 readprocesses or, for example, 2 read processes and 1 write process.

In a buffer organization model in accordance with the present invention,the total amount of buffer space available (which is limited by thetotal memory available and the buffer size), is divided into n sectionsof equal size, for a memory system with n banks. Each section has one ormore buffers. Sections and buffers are defined in the logical addressspace of the memory space available. The logical address space maps ontophysical memory locations. A single buffer can hold up to a number ofPDUs; e.g., m. All buffers are preferably of the same size. The numberof PDUs which can be stored in one buffer may be less than the length ofthe maximum packet length especially in a system which allows variablelength packets. In this case a packet is first split up into packetsegments, each packet segment having the same or less bits of data ascan be stored in one buffer. So if a packet has a length of l PDUs wherel is greater than m by p, whereby p is less than m, then the packet issplit into two packet segments, the first segment having length m PDUsfor instance, and the second segment has a length p. The consecutivePDUs of a buffer are allocated on banks in the memory system, so thatonly PDU j and PDU j+kn are in the same memory bank, for all k. Withoutany loss of generality, it is assumed that consecutive PDUs of a bufferare allocated in different memory banks, that is the buffer is stripedover the banks. The consecutive PDUs of a buffer may be striped intoconsecutive banks, for example. Section i can have as property that thefirst data PDU of section i is stored in bank i.

A separate buffer free-list is maintained per section, e.g. in asuitable register, which holds all free buffers in that section. As longas no free-list is empty, thus indicating that a section is completelyfilled up, the technique will work as outlined in this document.

As indicated above, for storing an incoming packet, it is first decidedif the packet has a length greater than m PDUs. If YES, the packet isfirst split into packet segments by a packet segment splitting unitwhich may be implemented in the packet receive unit (A). If NO thepacket is used as is. Each packet segment can fit in a single buffer.For every packet segment of the packet, the following procedure isfollowed when storing the packet. The packet segment is split into PDUs.A buffer is requested from the buffer management unit (D), for thatnumber of PDUs. The buffer management unit (D) keeps track of thesection from which it must allocate the next buffer, using the formulai′=(i+k)Mod n, where Mod is the modulus, n is the number of memorybanks, k is the number of PDUs in the current packet segment, i thesection in which the current packet segment is stored, and i′ thesection for the next packet segment.

In this way, incoming packets are striped over the memory banks, so thatall banks have exactly the same bandwidth of PDUs, regardless of thesize of the packet. This has as a consequence that the bandwidthallocated for storing packets is used, in a deterministic way, at fullcapacity. This is illustrated schematically in FIG. 3. The first packet“a” is split into two PDUs a₁ and a₂. These are temporarily stored insection 1 of the DRAM and are striped over banks 1 and 2 so that eachbank stores one PDU. The next packet “b” has two PDUs b₁ and b₂.Applying the formula i′=(i+k)Mod n whereby i=1, k=2 and n=4, the resultis i′=3, so b₁ and b₂ are stored in section 3 starting at the next banknot occupied in section 1, i.e. bank 3 and striping the PDUs over thebanks, i.e. temporarily storing these in banks 3 and 4. The packet “c”is 5 PDUs long. It is first split into two segments. The first segmentis split into 4 PDUs, c₁ to c₄. Applying i′=(i+k)Mod n with i=3 and k=2the PDUs c₁ to c₄ are stored in section 1 (as (3+2)Mod 4=1). As b₂ wasstored in bank 4, c₁ is stored in the next bank 1. The second segment ofpacket “c” is not split as it represents only one PDU “d”, this PDU “d”is stored in the section 1+4, i.e. in the first section again startingat bank 1. The next packet “e” is split into two PDUs which are storedin section 1+1, i.e. 2 starting in the bank immediately after d₁, i.e.bank 2.

To retrieve scheduled packets a scheduler (W, FIG. 4) independentlyorders the outgoing packets at its own rate, the scheduling-rate, whichmay not be a fixed rate, and it is assumed that the actual rate is notcorrelated to the packet length of the packet that is being scheduled.This scheduler may be included with the unit as shown in FIG. 1 or maybe external thereto. In the general case, the transmit order of packetsdiffers from the incoming order of packets. For instance, it can beassumed that it is pseudo-random, and the length of subsequent packetsthat are scheduled is uncorrelated.

Every scheduling decision eventually results in a series ofPDUReadRequests for contiguous banks, since the packet was stored thatway. However, the PDUReadRequests of subsequent scheduled packets are,in the general case, not contiguous.

It is also assumed that there is no correlation between the section andthe packet length (this is true if there is no correlation between thepacket lengths of two consecutive incoming packets). Under theseassumptions, it follows that statistically the PDUReadRequests areuniformly distributed over the banks.

Therefore, to increase the probability that all bank read-request-queuesare not empty, it is preferred if the number of packets that have beenscheduled and have submitted their PDUReadRequests in these queues. Thiscan be implemented using the architecture shown in FIG. 4. ATransmission Queue (Z) is used which may be implemented as a registerand which holds packet data before it is sent out. The Queue has aread-pointer (Y) and a reservation-pointer (X), and each queue-elementof the bank related queues (O-V) can hold one PDU of data. Each of thesequeues (O-V) may be implemented as a FIFO register. In total, the queuecan hold up to N PDUs of data. For the k PDUs of a packet that has beenscheduled, k queue-elements are reserved in the Transmission Queue atthe location of the reservation-pointer (X). The reservation-pointer isthen increased with k PDUs. If the queue has not enough free room, i.e.when read-pointer−reservation-pointer<k, then the scheduler (W) suspendsscheduling until there is enough free room. Next, every PDU of thepacket is translated into a PDUReadRequest that holds a pointer to thecorresponding queue-element in the transmission queue (Z). When the PDUis retrieved from memory, it is written in the queue into thisqueue-element. The read-pointer (Y) points to the queue-element thatcorresponds to the PDU that needs to be transmitted next. If thequeue-element already holds the PDU, it is transmitted, and theread-pointer is increased with 1. Otherwise the transmission stalls,until the PDU is available.

When the scheduler (W) schedules long packets or the transmission at theread-pointer stalls, the number of reserved queue-elements (betweenread- and reservation-pointer) increases. In that case, morePDUReadRequests are in the memory read-request queues, and thus theprobability increases that the memory read subsystem increases itsefficiency. Increasing the size of the Transmission Queue, N, increasesthe limit of simultaneous read-requests, and thus increases the overallperformance of the system.

The present invention may be implemented in hardware or, for example, insoftware using a processing engine such as a microprocessor or aprogrammable logic device (PLD) such as a PLA (programmable logicarray), PAL (programmable array logic), FPGA (field programmable gatearray). Examples of such implementations are provided below for purposesof illustration only.

An example of a hardware unit is shown in FIG. 5 configured as areceiver/transmitter circuit in accordance with an embodiment of thepresent invention. The circuit may be constructed as a VLSI chip. Threeon-chip static RAMs (SRAMs) may be used to provide buffering of thetransmission queue 20, the bank request FIFOs 16 and to hold the bufferfree list per bank 15. Packets are received by the packet receive block11. If the packet is larger than the memory space in one buffer, thisblock 11 splits the packet into packet segments. This block 11 alsosplits the packet segments (or packets if they are small enough) intoPDUs. The block 11 requests one buffer per packet segment from thebuffer manager block 14 which retrieves information about free buffersfrom the buffer free list memory 15 and allocates a free buffer. Thepacket receive block 11 sends the PDUs accompanied by a PDU locationaddress to the bank request FIFOs 16. The controller 17 for the off-chipmemory, e.g. an SDRAM 18, fetches these PDUs from the FIFOs 16 inaccordance with a schedule. For example, the controller 17 can pole eachFIFO 16-1 . . . 16-4 in turn. The controller 16 writes these PDUs intothe external memory 18 in accordance with the methods of the presentinvention, i.e. it stripes the PDUs of one packet or one packet segmentinto the memory banks in the external memory 18. A packet descriptor issent to the packet queue manager 12 from the packet receive unit 11. Thepacket queue manager 12 passes packet descriptors to the packet transmitrequest generator 13. The order of passing these requests may bedifferent from the receive order of the packets, e.g. the transmissionorder may be determined by packet priorities. The packet transmitgenerator 13 increments (or decrements) the reservation pointer of thetransmission queue in the on-chip SRAM 19 and generates PDU requests tothe bank request FIFOs 19. The controller 17 fetches the requests fromthe bank FIFOs 19 in accordance with a schedule, e.g. it polls each ofthe FIFOs 19-1 . . . 19-4 in turn. The controller 17 issues the requestsand sends the PDU data to the packet transmission queue manager 21. Thismanager 21 writes the PDU data in the correct transmission order in thePDU memory 20. The manager 21 maintains an incrementing (ordecrementing) read pointer to retrieve the packet data from the PDUmemory 20 for transmission. When the PDU memory 20 gets full, it slowsdown the request generator 13. When all the data of a packet buffer haveentered the transmission queue manager, the corresponding buffer isfreed.

Another example of a circuit in accordance with an embodiment of thepresent invention will be described with reference to FIG. 6 for areceiver/transmitter circuit 40. This circuit 40 may be constructed as aVLSI chip around an embedded microprocessor 27 such as an ARM7TDMI coredesigned by ARM Ltd., UK which may be synthesized onto a single chipwith the other components shown. A zero wait state SRAM memory 22 may beprovided on-chip as well as a cache memory 24. The SRAM memory 22 may beused for providing the various queues, registers and FIFO read and writequeues described above although itself not being large enough to storethe packet data. The interface to packet switched network 33 is providedby block 31. Packet data received by block 31 is passed to the processor27 for processing. An on-chip buffer 32 may be used to decouple theprocessor 27 from data transfer through the interface 31. Acounter/timer block 28 may be provided as well as an interruptcontroller 26. Software programs may be stored in an internal ROM (readonly memory) 23. Access to the off-chip (DRAM) memory banks 34 may beprovided through an external bus interface 25 with address, data andcontrol busses. The various blocks of circuit 40 are linked by suitablebusses 30.

The buffer control mechanisms of the present invention may beimplemented as software to run on processor 27. The procedures describedabove may be written as computer programs in a suitable computerlanguage such as C and then compiled for the specific processor in theembedded design. For example, for the embedded ARM core VLSI describedabove the software may be written in C and then compiled using the ARM Ccompiler and the ARM assembler.

Accordingly, the present invention also includes software computerprogram products for carrying out any of the methods of the presentinvention when run on a suitable processing engine as well as datacarriers for storing executable computer programs for carrying out anyof the methods of the present invention. However, it is important thatthose skilled in the art will appreciate that the mechanisms and methodsof the present invention are capable of being distributed as a programproduct in a variety of forms, and that the present invention appliesequally regardless of the particular type of signal bearing media usedto actually carry out the distribution. Examples of computer readablesignal bearing media include: recordable type media such as floppy disksand CD ROMs and transmission type media such as digital and analoguecommunication links.

While the invention has been shown and described with reference topreferred embodiments, it will be understood by those skilled in the artthat various changes or modifications in form and detail may be madewithout departing from the scope and spirit of this invention.

The invention therefore may be understood and described as a packetbuffering unit for a packet switched system comprising:

a packet receive unit for receiving packets from the network and forsplitting these packets into Packet Data Units (PDUs);

a plurality of memory banks;

a memory controller for striping at least some of the PDUs of a packetover the memory banks;

a packet management unit for retrieving PDUs stored in the memory banksand associated with a packet; and

transmission queue memory means for at least temporarily storing theretrieved PDUs in the sequence they are to be transmitted.

The invention is further understood as comprising a packet scheduler forscheduling a packet for transmission.

The packet buffering unit may also further comprise n memory banks,wherein the striping means stripes the PDUs over the memory banks inaccordance with n memory sections, each memory section comprising memoryspace from each memory bank, and the striping means allocates PDUs toeach section in accordance with i′=(i+k)Mod n where Mod is the modulus,n is the number of memory banks, k is the number of PDUs in a currentpacket, i is the section in which the current packet is stored, and i′the section for PDUs of the next packet.

Preferably, the striping means of the packet buffering unit allocatesconsecutive PDUs allocated to a buffer in consecutive memory banks andsection i has as property that the first PDU to be stored in section iis stored in bank i.

The packet buffering unit may further comprise a read request memorymeans for storing requests for PDUs stored in the memory banks.

The read request memory means may be configured as a FIFO.

The packet buffering unit can further comprise a read request generatorfor generating read requests.

The packet management unit of the packet buffering unit as set forthabove may further include a transmission queue manager for writing theretrieved PDUs in the sequence they are to be transmitted into thetransmission queue memory means.

In addition, the PDUs of a packet are striped over the memory banks areassociated with buffer, and the packet buffering unit further comprisesa buffer management unit for allocating a free buffer for PDUs of apacket.

The packet receive unit preferably comprises means for splitting apacket into packet segments if the packet is longer than can be storedin one buffer.

The packet receive unit further comprises means for splitting a packetsegment into PDUs.

The packet receive unit also further comprises means for generating aPDU location address for each PDU.

The packet buffering unit further preferably includes a write requestmemory means for storing the PDU location address and the PDU.

The write request memory means may be configured as a FIFO.

The packet buffering unit described above may be used in a node of apacket switched network.

The packet switch network in which the packet buffering unit is used cansupport different length data packets.

The invention may also be understood and described as a method ofbuffering packets in a packet switched system comprising:

-   -   receiving packets from the network and splitting these packets        into PDUs;    -   striping the data at least some of the PDUs of a packet over a        plurality of memory banks;    -   retrieving relevant data PDUs stored in the memory banks, and    -   at least temporarily storing the retrieved PDUs in the sequence        they are to be transmitted.

The method may further comprise striping the PDUs over memory banks inaccordance with n memory sections, each memory section comprising memoryspace from each memory bank, and allocating PDUs to each section inaccordance with i′=(i+k)Mod n where Mod is the modulus, n is the numberof memory banks, k is the number of PDUs in a current packet, i is thesection in which the current packet is stored, and i′ the section forPDUs of the next packet.

The method may further be described as further comprising allocatingconsecutive PDUs allocated to a buffer in consecutive memory banks,where section i has as a property that the first data PDU to be storedin section i is stored in bank i.

The methods of the invention may be implemented in a node of a packetswitched network which is adapted to execute the methods.

1. A packet buffering unit for a packet switched system comprising: apacket receive unit for receiving packets from the network and forsplitting these packets into Packet Data Units (PDUs); a plurality ofmemory banks coupled to said packet receive unit; a memory controllercoupled to said packet receive unit and said plurality of memory banksfor storing at least some of the PDUs of a packet over the memory banks;a packet management unit coupled to said packet receive unit forretrieving PDUs stored in the memory banks; and transmission queuememory means coupled to said packet management unit for at leasttemporarily storing the retrieved PDUs in the sequence they are to betransmitted; wherein the plurality of memory banks includes n memorybanks partitioned into s number of memory sections, each memory sectioncomprising memory space from each memory bank, and the memory controllerstores PDUs in each section in accordance with i′=(i+k)Mod n, where n isthe number of memory banks, k is the number of PDUs in a current packet,i is the section in which the current packet is stored, and i′ is thesection for PDUs of the next packet.
 2. A packet buffering unitaccording to claim 1, further comprising: a packet scheduler forscheduling a packet for transmission.
 3. A packet buffering unitaccording to claim 1, wherein: the memory controller stores consecutivePDUs in consecutive memory banks and section i has as property that thefirst PDU to be stored in section i is stored in bank i.
 4. A packetbuffering unit according to claim 3, further comprising: a read requestmemory means for storing requests for PDUs stored in the memory banks.5. A packet buffering unit according to claim 4, wherein: the readrequest memory means is configured as a FIFO.
 6. A packet buffering unitaccording to claim 5, further comprising a read request generatorcoupled to said read request memory means for generating read requests.7. A packet buffering unit according to claim 6, wherein: the packetmanagement unit comprises a transmission queue manager for writing theretrieved PDUs in the sequence they are to be transmitted into thetransmission queue memory means.
 8. A packet buffering unit according toclaim 7, further comprising: a PDU buffer, and a buffer management unitcoupled to the PDU buffer for allocating the buffer for PDUs of apacket.
 9. A packet buffering unit according to claim 1, wherein: thepacket receive unit includes means for generating a PDU location addressfor each PDU.
 10. A packet buffering unit according to claim 9, furthercomprising: a write request memory means coupled to said packet receiveunit for storing the PDU location address and the PDU.
 11. A packetbuffering unit according to claim 10, wherein: the write request memorymeans is configured as a FIFO.
 12. A packet buffering unit according toclaim 1, wherein the packets are not of uniform length.
 13. A method ofbuffering packets in a packet switched network comprising: receivingpackets from the network; splitting these packets into PDUs; storing atleast some of the PDUs of a packet over a plurality of memory banks;retrieving PDUs stored in the memory banks; and at least temporarilystoring the retrieved PDUs in the sequence they are to be transmitted;wherein the plurality of memory banks includes n memory bankspartitioned into s number of memory sections, each memory sectioncomprising memory space from each memory bank, and the storing of PDUsover the plurality of memory banks stores PDUs in each section inaccordance with i′=(i+k)Mod n, where n is the number of memory banks, kis the number of PDUs in a current packet, i is the section in which thecurrent packet is stored, and i′ is the section for PDUs of the nextpacket.
 14. A method according to claim 13, further comprising: storingconsecutive PDUs in consecutive memory banks, wherein section i has asproperty that the first PDU to be stored in section i is stored in banki.